High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip

This book introduces a novel framework for accurately modeling the errors in nanoscale technology and developing a smooth tool flow at high-level design abstractions to estimate error effects, which aids the development of high-level fault-tolerant techniques. In total, the book presents 6 solutions for reliability estimation (3 for fault injection and 3 for analytical estimation) and 5 techniques for reliability exploration (3 for architectural level and 2 for system-level). It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

• ISBN: 978-981-10-1072-9
• Editorial: Springer
• Encuadernacion: Cartoné
• Fecha Publicación: 09/10/2017
• Nº Volúmenes: 1
• Idioma: Inglés