CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design and test

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges andsolutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. Gives a process-aware perspective on SRAM circuit designand test Provides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of Static Noise Margin Introduces the concept of stability fault modelling Provides an Overview of specialized Design for Testability techniques for SRAM stability test Addresses soft-error considerations of SRAM design INDICE: From the contents Foreword. Preface. Acronyms. 1. Introduction AndMotivation. 2. SRAM Circuit Design And Operation. 3. SRAM Cell Stability: Definition, Modeling And Testing. 4. Traditional SRAM Fault Models And Test Practices. 5. Techniques For Detection Of SRAM Cells With Stability Faults. 6. SoftError In SRAMs: Sources, Mechanism And Mitigation Techniques. References. Index.

• ISBN: 978-1-4020-8362-4
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 200
• Fecha Publicación: 01/05/2008
• Nº Volúmenes: 1
• Idioma: Inglés