This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies,this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect. Describes design techniques to mitigate problems caused by variation. Includes techniques for designand implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperaturevariation tolerance INDICE: Introduction. On-Chip Communication. Interconnect Design Techniques. Design of Delay-Insensitive Current Sensing Interconnects. Enhancing Completion Detection Performance. Energy Efficient Semi-Serial Interconnect. Comparison of the Designed Interconnects. Circuit Techniques for PVT Variation Tolerance.
- ISBN: 978-1-4614-0130-8
- Editorial: Springer New York
- Encuadernacion: Cartoné
- Páginas: 192
- Fecha Publicación: 28/01/2012
- Nº Volúmenes: 1
- Idioma: Inglés