Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important designchallenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-artmethods to solve some of the most important and time-intensive problems encountered during NoC design. First book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs Presents an integrated flow to design interconnect architectures that can lead to faster time-to-market and design closure Shows evolution of design methods from complex crossbar based buses to NoCs INDICE: 1 Introduction. 2 Designing Crossbar Based Systems. 3 Netchip ToolFlow For NoC Design. 4 Designing Standard Topologies. 5 Designing Custom Topologies. 6 Supporting Multiple Applications. 7 Supporting Dynamic Application Patterns. 8 Timing-Error Tolerant NoC Design. 9 Analysis of NoC Error Recovery Schemes. 10 Fault-Tolerant Route Generation. 11 NoC Support for Reliable On-Chip Memories. 12 Conclusions and Future Directions.
- ISBN: 978-1-4020-9756-0
- Editorial: Springer
- Encuadernacion: Cartoné
- Páginas: 250
- Fecha Publicación: 01/04/2009
- Nº Volúmenes: 1
- Idioma: Inglés