Low-power high-level synthesis for nanoscale CMOScircuits

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the needfor analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. This book deals primarily with high-level (architectural or behavioral) leakage because the behavioral level is not as highly abstracted as thesystem level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. This book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Discusses high-level synthesis fundamentals Covers power dissipation sources in nano-CMOS transistors as well as power analysis, modeling and estimation techniques Includes information on power reduction fundamentals, specifically peak power reduction, transient power reduction and leakage power reduction INDICE: Introduction.- High-Level Synthesis Fundamentals.- Power Dissipation Sources in Nano-CMOS Transistors.- Power Analysis, Modeling, and EstimationTechniques.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.

• ISBN: 978-0-387-76473-3
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 200
• Fecha Publicación: 01/05/2008
• Nº Volúmenes: 1
• Idioma: Inglés