FSM based Digital Design with Verilog HDL covers the design and use of finitestate machines (FSMs) in digital systems, including stand-alone applications,as well as systems that use microprocessors, micro-controllers, memory controlled directly from the FSM, as well as other common situations found in practical digital systems. The emphasis is on obtaining a good understanding of FSMs, how they can be used, and where to use them. The authors set out a number ofpractical applications and worked through problems, and there is also an accompanying CD containing software tools for the capture, simulation and implementation of design solutions, with detailed instructions on how to use a particular tool. INDICE: CHAPTER 1 - THE BASICS Introduction What is a Finite State MachineNumber of States Number required for State Diagram - Frame 1.3 Mealy FSM Moore FSM Class C FSM Introduction to the State Diagram States, Transitions s - Frame 2.5 to 2.10 Chip Select t Cares A2.8 Shift Registers A2.9 Asynchronous Receiver Details for Section 4.7 Chapter 4 A2.9.1 Eleven Bit Shift Register for the Asynchronous Receiver Module A2.9.2 Divide by Eleven Counter A2.9.3 Complete Simulation of the Asynchronous Receiver System A2.10 Summary APPENDIX A3 - TUTORIAL ON THE USE OF VERILOG HDL TO SIMULATE AN FSM DESIGN A3.1 Introduction A3.2 Single Pulse with Memory Synchronous FSM Design A3.2.1 Specification A3.2.2 Block Diagram A3.2.3 State Diagram A3.2.4 Equations from the State Diagram A3.2.5 Translation into a Verilog Description A3.3 Test Bench Module and its Purpose A3.4 Using the Verilogger Simulator A3.4.1 Output from the Simulator A3.5 Summary APPENDIX A4 - IMPLEMENTING STATE MACHINES USING VERILOG BEHAVIOURALMODE A4.1 Introduction A4.2 Example 1- The Single Pulse with Memory FSM Revisited A4.3 The Memory Tester in Chapter 5, Section 5.6 Revisited A4.4 Summary
- ISBN: 978-0-470-06070-4
- Editorial: John Wiley & Sons
- Encuadernacion: Cartoné
- Páginas: 416
- Fecha Publicación: 29/02/2008
- Nº Volúmenes: 1
- Idioma: Inglés