Power distribution networks with on-chip decoupling capacitors

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of powerdistribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks. Describes power distribution systems and related design problems, including both circuit models and design techniques to allocate on-chip decoupling capacitors. Details effects of inductance on impedance characteristics of on-chippower distribution grids. Includes new material on inductance models for interdigitated structures, design strategies for multi-layer power grid networks, and advanced algorithms for computational power grid analysis. INDICE: Introduction. Inductive Properties of Electric Circuits. Properties of On-Chip Inductive Current Loops. Electromigration. Scaling Trends of On-Chip Power Distribution Noise. High Performance Power Distribution Systems. On-Chip Power Distribution Networks. Computer-Aided Design and Analysis. Closed Form Expressions for Fast IR Drop Analysis. Inductive Properties of On-Chip Power Distribution Grids. Variation of Grid Inductance with Frequency. Inductance/Area/Resistance Tradeoffs Inductance Model of Interdigitated Power and GroundDistribution Networks. On-chip Power Noise Reduction Techniques in High Performance ICs. Impedance/Noise Issues in On-Chip Power Distribution Networks. Impedance Characteristics of Multi-Layer Grids. Multi-Layer Interdigitated Power Distribution Networks. Multiple On-Chip Power Supply Systems. On-Chip Power Distribution Grids with Multiple Supply Voltages. Background for Decoupling Capacitance. Decoupling Capacitors for Multi-Voltage Power. Distribution Systems. Effective Radii of On-Chip Decoupling Capacitors. Efficient Placement of Distributed On-Chip Decoupling Capacitors. Simultaneous Co-Design of Distributed On-Chip Power Supplies and Decoupling Capacitors. Conclusions.

• ISBN: 978-1-4419-7870-7
• Editorial: Springer New York
• Encuadernacion: Cartoné
• Páginas: 618
• Fecha Publicación: 29/12/2010
• Nº Volúmenes: 1
• Idioma: Inglés