Power-aware testing and test strategies for low power devices

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications onmanufacturing test, and power-aware test is therefore increasingly becoming amajor consideration during design-for-test and test preparation for low powerdevices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices. Is the only comprehensive bookon power-aware test for (low power) circuits and systems Instructs readers how low-power devices can be tested safely without affecting yield and reliability Includes necessary background information on design for test and low-power design Incorporates detailed coverage of all levels of abstraction for power-aware testing of (low-power) circuits and systems Presents state-of-the-art industrial practices and EDA solutions INDICE: Introduction.-Fundamentals of VLSI Testing.-Power Issues During Test.-Low-Power Test Pattern Generation.-Power-Aware Design-for-Test.-Power-Aware BIST and Test Data Compression.-Power-Aware System-Level Test Planning.- LowPower Design Techniques and Test Implications.-Test Strategies for Multi-Voltage Designs.-Test Strategies for Gated Clock Designs.- Test of Power Management Structures.-EDA Solutions for Power-Aware Design-for-Test.

• ISBN: 978-1-4419-0927-5
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 390
• Fecha Publicación: 01/11/2009
• Nº Volúmenes: 1
• Idioma: Inglés