On and off-chip crosstalk avoidance in VLSI design

Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk,which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design. This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/orenergy consumption. Presents a novel way to combine chip and package design, reducing cross-talk so that VLSI systems can be designed to operate significantly faster Provides a comprehensive set of bus cross-talk cancellation techniques, both memoryless and memory-based Offers a battery of approaches for a VLSI designer to use, depending on the amount of cross-talk their design can tolerate, and the amount of area overhead they can afford INDICE: Introduction on On-Chip Crosstalk Avoidance. Preliminaries to On-Chip Crosstalk. Memoryless Crosstalk Avoidance Codes. CODEC Designs for Memoryless Crosstalk Avoidance Codes. Memory-based Crosstalk Avoidance Codes. Multi-valued Logic Crosstalk Avoidance Codes. Introduction to Off-Chip Crosstalk. Package Construction and Electrical Modeling. Preliminaries and Terminology. Analytical Model for Off-Chip Bus Performance. Optimal Bus Sizing. Bus Expansion Encoder. Bus Stuttering Encoder. Impedance Compensation. Future Trends and Applications. Summary of Off-Chip Crosstalk Avoidance.

• ISBN: 978-1-4419-0946-6
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 290
• Fecha Publicación: 01/02/2010
• Nº Volúmenes: 1
• Idioma: Inglés