INDICE: Acknowledgments.PART I. BASIC DIGITAL CIRCUITS.1. Gate-level combinational circuit.1.1 Introduction.1.2 General description.1.3 Basic lexical elements and data types.1.3.1 Lexical elements.1.4 Data types.1.4.1 Four-value system.1.4.2 Data type groups.1.4.3 Number representation.1.4.4 Operators.1.5 Program skeleton.1.5.1 Port declaration.1.5.2 Program body.1.5.3 Signal declaration.1.5.4 Another example.1.6 Structural description.1.7 Testbench.1.8 Bibliographic notes.1.9 Suggested experiments.1.9.1 Code for gate-level greater-thancircuit.1.9.2 Code for gate-level binary decoder.2. Overview of FPGA and EDA software.2.1 Introduction.2.2 FPGA.2.2.1 Overview of a general FPGA device.2.2.2 Overview of the Xilinx Spartan-3 devices.2.3 Overview of the Digilent S3 board.2.4 Development flow.2.5 Overview of the Xilinx ISE project navigator.2.6 Short tutorial on ISE project navigator.2.6.1 Create the design project and HDL codes.2.6.2 Create a testbench and perform the RTL simulation.2.6.3 Add a constraint file and synthesize and implement the code.2.6.4 Generate and download the configuration file to an FPGA device.2.7 Short tutorial on the ModelSim HDL simulator.2.8 Bibliographic notes.2.9 Suggested experiments.2.9.1 Gate-level greater-than circuit.2.9.2 Gate-level binary decoder.3. RT-level combinational circuit.3.1 Introduction.3.2 Operators.3.2.1 Arithmetic operators.3.2.2 Shift operators.3.2.3 Relational and equality operators.3.2.4 Bitwise, reduction, and logical operators.3.2.5 Concatenation and replication operators.3.2.6 Conditional operators.3.2.7 Operator precedence.3.2.8 Expression bit-length adjustment.3.2.9 Synthesis of z and x values.3.3 Always block for combinational circuit.3.3.1 Basic syntax and behavior.3.3.2 Procedural assignment.3.3.3 Variable data types.3.3.4 Simple examples.3.4 If statement.3.4.1 Syntax.3.4.2 Examples.3.5 Case statement.3.5.1 Syntax.3.5.2 Examples.3.5.3 The casez and casex statements.3.5.4 The full case and parallel case.3.6 Routing structure of conditional control constructs.3.6.1 Priority routing network.3.6.2 Multiplexing network.3.7 General coding guidelines for always block 60.3.7.1 Common errors in combinational circuit codes 60.3.7.2 Guidelines.3.8 Parameter and constant.3.8.1 Constant.3.8.2 Parameter.3.8.3 Use of parameter in Verilog-1995.3.9 Design examples.3.9.1 Hexadecimal digit to seven-segment LED decoder.3.9.2 Sign-magnitude adder.3.9.3 Barrel shifter.3.9.4 Simplified floating-point adder.3.10 Bibliographic notes.3.11 Suggested experiments.3.11.1 Multi-function barrel shifter.3.11.2 Dual-priority encoder.3.11.3 BCD incrementor.3.11.4 Floating-point greater-than circuit.3.11.5 Floating-point and signed integer conversion circuit.3.11.6 Enhanced floating-point adder.4. Regular Sequential Circuit.4.1 Introduction.4.1.1 D FF and register.4.1.2 Synchronous system.4.1.3 Code development.4.2 HDL code of the FF and register.4.2.1 D FF.4.2.2 Register.4.2.3 Registerfile.4.2.4 Storage components in a Spartan-3 deviceXilinx specific.4.3 Simpledesign examples.4.3.1 Shift register.4.3.2 Binary counter and variant.4.4 Testbench for sequential circuits.4.5 Case study.4.5.1 LED time-multiplexing circuit.4.5.2 Stopwatch 10.4.5.3 FIFO buffer 110.4.6 Bibliographic notes.4.7 Suggested experiments.4.7.1 Programmable square wave generator.4.7.2 PWM and LED dimmer.4.7.3 Rotating square circuit.4.7.4 Heartbeat circuit.4.7.5 Rotating LED banner circuit.4.7.6 Enhanced stopwatch.4.7.7 Stack.5. FSM.5.1 Introduction.5.1.1 Mealy and Moore outputs.5.1.2 FSM representation.5.2 FSM code development.5.3 Design examples.5.3.1 Rising-edge detector.5.3.2 Debouncing circuit.5.3.3 Testing circuit.5.4 Bibliographic notes.5.5 Suggested experiments.5.5.1 Dual-edge detector.5.5.2 Alternative debouncing circuit.5.5.3 Parking lot occupancy counter.6. FSMD.6.1 Introduction.6.1.1 Single RT operation.6.1.2 ASMD chart.6.1.3 Decision box with a register.6.2 Code development of an FSMD.6.2.1 Debouncing circuit based on RT methodology.6.2.2 Code with explicit data path components.6.2.3 Code with implicit data path components.6.2.4 Comparison.6.2.5 Testing circuit.6.3 Design examples.6.3.1 Fibonacci number circuit.6.3.2 Division circuit.6.3.3 Binary-to-BCD conversion circuit.6.3.4 Period counter.6.3.5 Accurate low-frequency counter.6.4 Bibliographic notes.6.5 Suggested experiments.6.5.1 Alternative debouncing circuit.6.5.2 BCD-to-binary conversion circuit.6.5.3 Fibonacci circuit with BCD I/O: design approach.6.5.4 Fibonacci circuit withBCD I/O: design approach.6.5.5 Auto-scaled low-frequency counter.6.5.6 Reaction timer.6.5.7 Babbage difference engine emulation circuit.7. Selected Topics of Verilog.7.1 Blocking versus nonblocking assignment.7.1.1 Overview.7.1.2 Combinational circuit.7.1.3 Memory element.7.1.4 Sequential circuit with mixed blocking and nonblocking.assignments.7.2 Alternative coding style for sequentialcircuit.7.2.1 Binary counter.7.2.2 FSM.7.2.3 FSMD.7.2.4 Summary.7.3 Use of the signed data type.7.3.1 Overview.7.3.2 Signed number in Verilog-1995.7.3.3 Signed number in Verilog-2001.7.4 Use of function in synthesis.7.4.1 Overview.7.4.2 Examples.7.5 Additional constructs for testbench development.7.5.1 Always block and initial block.7.5.2 Procedural statements.7.5.3 Timing control.7.5.4Delay control.7.5.5 Event control.7.5.6 Wait statement.7.5.7 Timescale directive.7.5.8 System functions and tasks.7.5.9 User defined functions and tasks.7.5.10 Example of a comprehensive testbench.7.6 Bibliographic notes.7.7 Suggested experiments.7.7.1 Shift register with blocking and nonblocking assignments.7.7.2 Alternative coding style for BCD counter.7.7.3 Alternative coding style for FIFO buffer.7.7.4 Alternative coding style for Fibonacci circuit.7.7.5 Dual-mode comparator.7.7.6 Enhanced binary counter monitor.7.7.7 Testbench for FIFO buffer.PART II. I/O MODULES.8. UART.8.1 Introduction.8.2 UART receiving subsystem.8.2.1 Oversampling procedure.8.2.2 Baud rate generator.8.2.3 UART receiver.8.2.4 Interface circuit.8.3 UART transmitting subsystem.8.4 Overall UART system.8.4.1 Complete UART core.8.4.2 UART verification configuration.8.5 Customizing a UART.8.6 Bibliographic notes.8.7 Suggested experiments.8.7.1 Full-featured UART.8.7.2 UART with an automatic baud rate detection circuit.8.7.3 UART with an automatic baud rate and parity detection circuit.8.7.4 UART-controlledstopwatch.8.7.5 UART-controlled rotating LED banner.9. PS2 Keyboard.9.1 Introduction.9.2 PS2 receiving subsystem.9.2.1 Physical interface of a PS2 port.9.2.2 Device-to-host communication protocol.9.2.3 Design and code.9.3 PS2 keyboard scan code.9.3.1 Overview of the scan code.9.3.2 Scan code monitor circuit.9.4 PS2 keyboard interface circuit.9.4.1 Basic design and HDL code.9.4.2 Verification circuit.9.5 Bibliographic notes.9.6 Suggested experiments.9.6.1 Alternative keyboard interface I.9.6.2 Alternative keyboard interface II.9.6.3 PS2 receiving subsystem with watchdog timer.9.6.4 Keyboard-controlled stopwatch.9.6.5Keyboard-controlled rotating LED banner.10. PS2 Mouse.10.1 Introduction.10.2 PS2 mouse protocol.10.2.1 Basic operation.10.2.2 Basic initialization procedure.10.3 PS2 transmitting subsystem.10.3.1 Host-to-PS2-device communication protocol.10.3.2 Design and code.10.4 Bidirectional PS2 interface.10.4.1 Basic design and code.10.4.2 Verification circuit.10.5 PS2 mouse interface.10.5.1 Basic design.10.5.2 Testing circuit.10.6 Bibliographic notes.10.7 Suggested experiments.10.7.1 Keyboard control circuit.10.7.2 Enhanced mouse interface.10.7.3 Mouse-controlled seven-segment LED display.11. External SRAM.11.1 Introduction.11.2 Specification of the IS61LV25616AL SRAM.11.2.1 Block diagram and I/O signals.11.2.2 Timing parameters.11.3 Basic memory controller.11.3.1 Block diagram.11.3.2 Timing requirement.11.3.3 Register file versus SRAM.11.4 A safe design.11.4.1 ASMD chart.11.4.2 Timing analysis.11.4.3 HDL implementation.11.4.4 Basictesting circuit.11.4.5 Comprehensive SRAM testing circuit.11.5 More aggressive design 288.11.5.1 Timing issues.11.5.2 Alternative design I.11.5.3 Alternative design II.11.5.4 Alternative design III.11.5.5 Advanced FPGA featuresXilinxspecific.11.6 Bibliographic notes.11.7 Suggested experiments.11.7.1 Memory with a 512K-by-16 configuration.11.7.2 Memory with a 1M-by-8 configuration.11.7.3 Memory with an 8M-by-1 configuration.11.7.4 Expanded memory testing circuit.11.7.5 Memory controller and testing circuit for alternative design I.11.7.6 Memory controller and testing circuit for alternative design II.11.7.7 Memory controller and testing circuit for alternative design III.11.7.8 Memory controller with DCM.11.7.9 High-performance memory controller.12. Xilinx Spartan-3 Specific Memory.12.1 Introduction.12.2 Embedded memory of Spartan-3 device.12.2.1 Overview.12.2.2 Comparison.12.3 Method to incorporate memory modules.12.3.1 Memory module via HDL component instantiation.12.3.2 Memory module via Core Generator.12.3.3 Memory module via HDL inference.12.4 HDL templates for memory inference.12.4.1 Single-port RAM.12.4.2 Dual-port RAM.12.4.3 ROM.12.5 Bibliographic notes.12.6 Suggested experiments.12.6.1 Block-RAM-based FIFO.12.6.2 Block-RAM-based stack.12.6.3 ROM-based sign-magnitude adder.12.6.4 ROM based sin(x)function.12.6.5 ROM-based sin(x) and cos(x) functions.13. VGA controller I: graphic.13.1 Introduction.13.1.1 Basic operation of a CRT.13.1.2 VGA port of the S3 board.13.1.3 Video controller.13.2 VGA synchronization.13.2.1 Horizontal synchronization.13.2.2 Vertical synchronization.13.2.3 Timing calculation of VGA synchronization signals.13.2.4 HDL implementation.13.2.5 Testing circuit.13.3 Overview of the pixel generation circuit.13.4 Graphic generation with an object-mapped scheme.13.4.1 Rectangular objects 320.13.4.2 Non-rectangular object.13.4.3 Animated object.13.5 Graphic generation with a bit-mapped scheme.13.5.1 Dual-port RAM implementation.13.5.2 Single-port RAM implementation.13.6 Bibliographic notes.13.7 Suggested experiments.13.7.1 VGA test pattern generator.13.7.2 SVGA mode synchronization circuit.13.7.3 Visible screen adjustment circuit.13.7.4 Ball-in-a-box circuit.13.7.5 Two-balls-in-a-box circuit.13.7.6 Two-player pong game.13.7.7 Breakout game.13.7.8 Full-screen dot trace.13.7.9 Mouse pointer circuit.13.7.10 Small-screen mouse scribble circuit.13.7.11 Full-screen mouse scribble circuit.14. VGA controller II: text.14.1 Introduction.14.2 Text generation.14.2.1 Character as a tile.14.2.2 Font ROM.14.2.3 Basic text generation circuit.14.2.4 Font display circuit.14.2.5 Font scaling.14.3 Full-screen text display.14.4 The complete pong game.14.4.1 Text subsystem.14.4.2 Modified graphic subsystem.14.4.3 Auxiliary counters.14.4.4 Top-level system.14.5Bibliographic notes.14.6 Suggested experiments.14.6.1 Rotating banner.14.6.2 Underline for the cursor.14.6.3 Dual-mode text display.14.6.4 Keyboard text entry.14.6.5 UART terminal.14.6.6 Square wave display.14.6.7 Simple four-trace logic analyzer.14.6.8 Complete two-player pong game.14.6.9 Complete breakout game.PART III. PICOBLAZE MICROCONTROLLERXILINX SPECIFIC.15. PicoBlaze Overview.15.1 Introduction.15.2 Customized hardware and customized software.15.2.1 From special-purpose FSMD to general-purpose microcontroller.15.2.2 Application of microcontroller.15.3 Overview of PicoBlaze.15.3.1 Basic organization.15.3.2 Top-level HDL modules.15.4 Development flow.15.5 Instruction set.15.5.1 Programming model.15.5.2 Instruction format.15.5.3 Logical instructions.15.5.4 Arithmetic instructions.15.5.5 Compare and test instructions.15.5.6 Shift and rotate instructions.15.5.7 Data movement instructions.15.5.8 Program flow control instructions.15.5.9 Interrupt related instructions.15.6 Assembler directives.15.6.1 The KCPSM3 directives.15.6.2 The PBlazeIDE directives.15.7 Bibliographic notes.16. PicoBlaze Assembly Code Development.16.1 Introduction.16.2 Useful codesegments.16.2.1 KCPSM3 conventions.16.2.2 Bit manipulation.16.2.3 Multiple-byte manipulation.16.2.4 Control structure.16.3 Subroutine development.16.4 Program development.16.4.1 Demonstration example.16.4.2 Program documentation.16.5Processing of the assembly code.16.5.1 Compiling with KCSPM3.16.5.2 Simulation by PBlazeIDE.16.5.3 Reloading code via the JTAG port.16.5.4 Compiling by PBlazeIDE.16.6 Syntheses with PicoBlaze.16.7 Bibliographic notes.16.8 Suggested experiments.16.8.1 Signed multiplication.16.8.2 Multi-byte multiplication.16.8.3 Barrel shift function.16.8.4 Reverse function.16.8.5 Binary-to-BCD conversion.16.8.6 BCD-to-binary conversion.16.8.7 Heartbeat circuit.16.8.8 Rotating LEDcircuit.16.8.9 Discrete LED dimmer.17. PicoBlaze I/O Interface.17.1 Introduction.17.2 Output port.17.2.1 Output instruction and timing.17.2.2 Output interface.17.3 Input port.17.3.1 Input instruction and timing.17.3.2 Input interface.17.4 Square program with a switch and seven-segment LED display interface.17.4.1 Output interface.17.4.2 Input interface.17.4.3 Assembly code development.17.4.4 HDL code development.17.5 Square program with a combinational multiplierand UART console.17.5.1 Multiplier interface.17.5.2 UART interface.17.5.3 Assembly code development.17.5.4 HDL code development.17.6 Bibliographic notes.17.7 Suggested experiments.17.7.1 Low-frequency counter I.17.7.2 Low-frequency counter II.17.7.3 Auto-scaled low-frequency counter.17.7.4 Basic reaction timerwith a software timer.17.7.5 Basic reaction timer with a hardware timer.17.7.6 Enhanced reaction timer 450.17.7.7 Small-screen mouse scribble circuit 450.17.7.8 Full-screen mouse scribble circuit 450.17.7.9 Enhanced rotating banner 450.17.7.10 Pong game 450.17.7.11 Text editor 450.18. PicoBlaze Interrupt Interface.18.1 Introduction.18.2 Interrupt handling in PicoBlaze.18.2.1 Software processing.18.2.2 Timing.18.3 External interface.18.3.1 Single interrupt request.18.3.2 Multiple interrupt requests.18.4 Software development considerations.18.4.1 Interrupt as an alternative scheduling scheme.18.4.2 Development of an interrupt service routine.18.5 Design example.18.5.1 Interrupt interface.18.5.2Interrupt service routine development.18.5.3 Assembly code development.18.5.4HDL code development.18.6 Bibliographic notes.18.7 Suggested experiments.18.7.1 Alternative timer interrupt service routine.18.7.2 Programmable timer.18.7.3 Set-button interrupt service routine.18.7.4 Interrupt interface with two requests.18.7.5 Four-request interrupt controller.Appendix A: Sample Verilog templates.A.1 Numbers and operators.A.1.1 Sized and unsized numbers.A.1.2 Operators.A.2 General Verilog constructs.A.2.1 Overall code structure.A.2.2 Component instantiation.A.3 Routing with conditional operator and if and case statements.A.3.1 Conditional operator and if statement.A.3.2 Case statement.A.4 Combinational circuit using always block.A.4.1 Always block without default output assignment.A.4.2 Always block with default output assignment.A.5 Memory Components.A.5.1 Register template.A.5.2 Register file.A.6 Regular sequential circuits.A.7 FSM.A.8 FSMD.A.9 S3 board constraint file (s3.ucf) 4.References.Topic Index
- ISBN: 978-0-470-18532-2
- Editorial: John Wiley & Sons
- Encuadernacion: Cartoné
- Páginas: 486
- Fecha Publicación: 01/07/2008
- Nº Volúmenes: 1
- Idioma: Inglés