Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describeproperties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an ‘under-the-hood’ view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage ofthe modern assertion languages, with a focus on obtaining the highest performance from assertion checkers. Efficient synthesis of assertion checkers for the main assertion languages (PSL and SVA) Applications in verification, emulation, post-fabrication debugging, on-line monitoring, with a unique ‘under-the-hood’ view A missing link between the literature on assertion languages and pre-made checker libraries Extensive benchmarks and verification of assertion checkers, with examples of real-world circuit checkers INDICE: 1 Introduction. 2 Assertions and the Verification Landscape. 3 Basic Techniques Behind Assertion Checkers. 4 PSL and SVA Assertion Languages. 5 Automata for Assertion Checkers. 6 Construction of PSL Assertion Checkers. 7 Enhanced Features and Uses of PSL Checkers. 8 Evaluating and Verifying PSL Assertion Checkers. 9 Checkers for SystemVerilog Assertions. 10 Conclusions and FutureWork. A Example for Up-down Counter. References. Index.
- ISBN: 978-1-4020-8585-7
- Editorial: Springer
- Encuadernacion: Cartoné
- Páginas: 280
- Fecha Publicación: 01/06/2008
- Nº Volúmenes: 1
- Idioma: Inglés