Static timing analysis for nanometer designs: a practical approach

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology. Provides a reference for engineers in the field of static timing analysis for semiconductors Discusses the underlying theoretical background as well as in-depth coverage of timing verification using static timing analysis Covers topics suchas CMOS logic gates, cell library, timing arcs, waveform slew, and cell capacitance, among others INDICE: Introduction.- STA Concepts.- Standard Cell Library.- InterconnectParasitics.- Delay Calculation.- Noise and Crosstalk.- Configuring the Environment: Preparing for STA.- Timing Verification.- Interface Analysis.- Robust Verification.

• ISBN: 978-0-387-93819-6
• Editorial: Springer
• Encuadernacion: Cartoné
• Páginas: 572
• Fecha Publicación: 01/05/2009
• Nº Volúmenes: 1
• Idioma: Inglés