Verification Methodology Manual for SystemVerilog

Offers users the first resource guide that combines both the methodology and basics of SystemVerilog

Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.

Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.

• ISBN: 978-1-4614-9813-1
• Editorial: Springer
• Encuadernacion: Rústica
• Fecha Publicación: 05/12/2014
• Nº Volúmenes: 1
• Idioma: Inglés