Wafer-level testing and test during burn-in for integrated circuits
Bahukudumbi, Sudarshan
94,04 €(IVA inc.)
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures.
- ISBN: 978-1-59693-989-9
- Editorial: Artech House
- Encuadernacion: Cartoné
- Páginas: 210
- Fecha Publicación: 01/04/2010
- Nº Volúmenes: 1
- Idioma: Inglés