Microprocessor architecture: from simple pipelines to chip multiprocessors

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: * The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorderbuffers * Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations * Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors * State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity. "Professor Baer has developed an extremely appropriate and timely textbook for computer architecture, with a focus on how processors work, and how selectmicro-architectural features work. He is an excellent teacher, and has effectively presented and explained the concepts. The text covers all the major subjects necessary for a semester-long course in computer architecture." Patrick Crowley, Washington University in St. Louis INDICE: 1. Introduction; 2. The basics; 3. Superscalar processors; 4. Front-end: branch prediction, instruction fetching, and register renaming; 5. Back-end: instruction scheduling, memory access instructions, and clusters; 6. Thecache hierarchy; 7. Multiprocessors; 8. Multithreading and (chip) multiprocessors; 9. Current limitations and future challenges

• ISBN: 978-0-521-76992-1
• Editorial: Cambridge University
• Encuadernacion: Cartoné
• Páginas: 382
• Fecha Publicación: 01/03/2010
• Nº Volúmenes: 1
• Idioma: Inglés