Low power design with high-level power estimationand power-aware synthesis

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-levelsynthesis. Readers will learn to apply such techniques to enable design flowsresulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design. Shows specific techniques for ASICs as well as FPGAbased SoC designs, allowing readers to evaluate and explore various possible alternatives. Covers techniques from RTL/gate-level to hardware software co-design INDICE: Introduction. Related Work. Background. Architectural Selection using High Level Synthesis. Statistical Regression Based Power Models. Coprocessor Design Space Exploration Using High Level Synthesis. Regression-based Dynamic Power Estimation for FPGAs. High Level Simulation Directed RTL Power Estimation. Applying Verification Collaterals for Accurate Power Estimation. Power Reduction using High-Level Clock-gating. Model-Checking to exploit Sequential Clock-gating. System Level Simulation Guided Approach for Clock-gating. Conclusions.

• ISBN: 978-1-4614-0871-0
• Editorial: Springer New York
• Encuadernacion: Cartoné
• Páginas: 176
• Fecha Publicación: 28/10/2011
• Nº Volúmenes: 1
• Idioma: Inglés